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M-986-2A1
MF Transceiver
Features * Direct A-Law or -Law PCM digital input * 2.048 Mb/s clocking * Operates with standard codecs for analog interfacing * Microprocessor read/write interface * Binary or 2-of-6 data formats * Dual-channel * 5 volt power Description The M-986-2A1 dual channel MF Transceiver contains all the logic necessary to transmit and receive (North American) CCITT Region 1 multifrequency signals on one integrated circuit (IC). Operating with a 20.48 MHz crystal, the M-986 is capable of providing a direct digital interface to a mlaw or A-law encoded PCM digital input. Each channel can be connected to an analog source using a coderdecoder (codec) as shown in the Block Diagram below. The M-986 is configured and controlled through an integral coprocessor port.
Applications * * * * * Test equipment Trunk adapters Paging terminals Traffic recorders PBXs
Ordering Information Part #
M-986-2A1P M-986-2A1PL
Description
40-pin plastic DIP 44-pin PLCC
Block Diagram
DS-M986-2A1
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M-986-2A1
Absolute Maximum Ratings Over Specified Temperature Range
Supply voltage range, VCC Input voltage range Output voltage range Ambient air temperature range Storage temperature range -0.3 V to 7 V -0.3 V to 15 V -0.3 V to 15 V 0 to 150C -45C to 150C Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability.
Function Description The M-986-2A1 can be set up for various modes of operation by writing two configuration bytes to the coprocessor port. The format of the two configuration bytes is shown in the Configuration Table on page 3 and the configuration options are described in the following paragraphs. Configuration Options External/Internal Codec Clock (ECLK): If external codec clocking is selected, an external clocking source provides an 8 kHz transmit framing clock and an 8 kHz receive framing clock. It also provides a serial bit clock with a frequency that is a multiple of 8 kHz between 216 kHz and 2.496 MHz for exchange of data via the serial ports. When internal codec clocking is selected, the M-986-2A1 provides an 8 kHz framing clock and a 2.048 MHz serial bit clock. 2 of 6/Binary Input/Output (IOM): When the 2-of-6 input/output is selected, the M-986-2A1 encodes the received R1 MF tone pair into a 6-bit format, where each bit represents one of the six possible frequencies. A logic high level indicates the presence of a frequency. The digital input to the M-986-2A1 that selects the transmitted R1 MF tone pair must also be coded in the 2-of-6 format. Electrical Characteristics/Temperature Range
When binary input/output is selected, the M-986-2A1 encodes the received R1 MF tone pair into a 4 bit binary format. The digital input to the M-986-2A1 that selects the transmitted R1 MF tone pair must also be coded in a 4 bit binary format. Enable/Disable Channel (ENC): When a channel is disabled, the receiver does not process its codec input for R1 MF tones, and the transmitter does not respond to transmit commands. If a transmit command is given while the channel is enabled, the "tone off" command must be given before the channel is disabled. Disabling the channel does not automatically shut off the transmitter. When a channel is enabled, the receiver and transmitter for that channel function normally. Long/Short KP Tone Detection Time (KPL): When long KP tone detection is selected, the minimum on time for the KP tone to be detected is 55 milliseconds. When short KP tone detection is selected, the minimum on time for the KP tone to be detected is 30 milliseconds (the same as the minimum on time for the rest of the MF tones). Enable MF Tone Detection After Reception of KP (KPEN): When this feature is enabled, MF tone detection is enabled after reception of the KP tone, and disabled after reception of ST, ST1, ST2, or ST3 tones. When this feature is disabled, MF tone detection is always enabled. Select A or -law input/output (AMU) for A-law encoding, this bit is set to a 1, for -law encoding it is set to 0.
Typ 2.4 VCC -0.4 Max 50 3 0.3 25 15 25 10 Unit 75 0.6 20 -20 20 50 -
ICC VOH VOL IOZ II CI CO
Parameter Test ConditionsMin Supply current f = 20.5 MHz, VCC = 5.5V, TA = 0 to 70 C High-level output voltage IOH = MAX IOH = 20 A Low-level output voltage IOL = MAX Off-state output current VCC = MAX VO = 2.4 V VO = 0.4 V Input current VI = VSS to VCC Except CLKIN CLKIN Input capacitance Data bus f = 1 MHz, all other pins 0 V All others Output capacitance Data bus All others
mA V V V A A A A pF pF pF pF
Rev. 3
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M-986-2A1
Configuration
Configuration Byte 1 Bit 7 0 ECLK IOM ENC1 KPL1 KPEN1 Bit 6 0 Bit 5 ECLK Channels 1 & 2 Channels 1 & 2 Channel 1 Channel 1 Channel 1 Bit 4 IOM Bit 3 ENCI Bit 2 KPL1 Bit 1 KPEN1 Bit 0 0
1 = External codec clock; 0 = Internal codec clock 1 = Binary input/output; 0 = 2-of-6 input/output 1 = Enable channel; 0 = Disable channel 1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP 1 = Enable MF tone detection after KP detection; 0 = MF tone detection always on Configuration Byte 2
Bit 7 0 AMU ENC2 KPL2 KPEN2
Bit 6 1
Bit 5 0 Channels 1 & 2 Channel 2 Channel 2 Channel 2
Bit 4 AMU
Bit 3 ENC2
Bit 2 KPL2
Bit 1 KPEN2
Bit 0 0
1 = A-law Encoding, 0 = m-law Encoding 1 = Enable channel; 0 = Disable channel 1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP 1 = Enable MF tone detection after KP detection; 0 = MF tone detection always
Initial Configuration: The configuration of the M-9862A1 immediately after a reset will be as follows: * channel disabled * 2-of-6 input/output * external serial and serial frame clocks. Also, the M-986-2A1 will place a 00 hex on the coprocessor port to indicate to the host processor that it is working. Transmit Tone Command The transmit tone command allows the host processor to transmit any two of the 6 R1 MF frequencies. The format of the command depends on whether the M986 is configured for binary format or 2-of-6 format.
Coprocessor Port Commands are written to the M-986 via the coprocessor port, and data indicating the received R1 MF tone is read from the coprocessor port. Writing to the Coprocessor Port: The following sequence describes writing a command to the M-986. (1) The WR signal is driven low by the host processor. (2) The RBLE (receive buffer latch empty) signal transitions to a logic high level. (3) Data is written from D7-D0 to the receive buffer latch (D7-D0) when the WR signal goes high. (4) The RBLE signal transitions to a logic low level after the M-986 reads the data. This signals the host processor that the receive buffer is empty. Note: The RBLE should be low before writing to the coprocessor.
Recieved Tone Detection When a tone is detected by the M-986, the TBLF output goes low, indicating reception of the tone to the host processor. The host processor can determine which tone was detected and which channel the tone was detected on by reading data from the M-986 coprocessor port. The M-986 will return a single byte indicating the tone received and the channel that the tone was received on. The format of the returned byte depends on whether the M-986 is configured for binary or 2-of-6 coding.
Reading the Coprocessor Port: The following sequence describes reading received tone information from the coprocessor port. (1) The TBLF (transmit buffer latch full) port pin on the M-986 goes low indicating the reception of a tone. (2) The host processor detects the low logic level on the TBLF pin either by polling a connected port pin or by an interrupt. (3) The host processor drives the RD signal low. (4) The TBLF (transmit buffer latch full) signal transition to a logic high level.
Rev. 3
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M-986-2A1
(5) Data is driven onto D7-D0 by the M-986 until the RD signal is driven high by the host processor. Clock Characteristics and Timing Internal Clock Option: The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be 20.48 MHz, fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. External Clock Option: An external frequency source can be used by injecting the frequency directly in X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in External Frequency Specifications table on page 6. Flammability/Reliability Specifications Reliability: Flammability: 185 FITS failures/billion hours Passes UL 94 V-0 tests
2 of 6 Coding Format
Byte Bit 7 Transmit tone command 1 Receive tone return 0 CHN: 1 = channel 2; 0 = channel 1 R1 MF Frequencies: Bit name Frequency (Hz) F6 F5 F4 1700 1500 1300 Bit 6 CHN CHN Bit 5 F6 F6 Bit 4 F5 F5 Bit 3 F4 F4 Bit 2 F3F2 F3F2 Bit 1 F1 F1 Bit 0
Bit name F3 F2 F1
Frequency (Hz) 1100 900 700
Binary Coding Format
Byte Bit 7 Transmit tone command 1 Receive tone return 0 CHN: 1 = channel 2; 0 = channel 1 R1 MF Frequencies: ABCD Frequencies (Hz) 0000 0001 0010 0011 0100 0101 0110 0111 Tone off 700 & 900 700 & 1100 900 & 1100 700 & 1300 900 & 1300 1100 & 1300 700 & 1500 Bit 6 CHN CHN Bit 5 0 0 Bit 4 0 0 Bit 3 A A Bit 2 B B Bit 1 C C Bit 0 D D
Name Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7
ABCD 1000 1001 1010 1011 1100 1101 1110 1111
Frequencies (Hz) 900 & 1500 1100 & 1500 1300 & 1500 700 & 1700 900 & 1700 1100 & 1700 1300 & 1700 1500 & 1700
Name Digit 8 Digit 9 Digit 0 ST3 ST1 KP ST2 ST
Rev. 3
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M-986-2A1
Signal Description
Signal D15-D8 D7-D0 TBLF RBLE HI/LO BIO RD Pin 18-11 19-26 40 1 2 9 32 I/O/Z I/O/Z I/O/Z O O I I I/O Description Unused. Leave open. 8-bit coprocessor latch. Transmit buffer latch full flag. Receive buffer latch empty flag. Latch byte select pin. Tie low. Unused. Leave open. Used by the external processor to read from the coprocessor latch by driving the RD line active (low), thus enabling the output latch to drive the latched data. When the data has been read, the external device must bring the RD line high. Unused. Leave open. Microcomputer mode select pin. Tie low. Coprocessor mode select pin. Tie low. Reset input for initializing the device. When an active low is placed on RS pin for a minimum of five clock cycles, RD and WR are forced high, and the data bus (LD7 through LD0) goes to a high impedance state. The serial port clock and transmit outputs also go to the high impedance state. Used by the external processor to write data to the coprocessor port. To write data the external processor drives the WR line low, places data on the data bus, and then drives the WR line high to clock the data into the on-chip latch. Watchdog signal. Toggles at least once every 10 milliseconds when the processor is functioning properly. If the pin is not toggled at least once every 10 ms, the processor is lost and should be reset. System clock output (one-fourth crystal/CLKIN frequency, nominally 5.12 MHz). Ground pin. 5V supply pin. Crystal output pin for internal oscillator. If the internal oscillator is not used, this pin should be left unconnected. Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin for the external oscillator (CLKIN). Serial-port receive-channel inputs. 2.048 MHz serial data is received in the receive registers via these pins. DR0 = channel 1; DR1 = channel 2. 8 kHz internal serial-port framing output. If internal clocking is selected, serial-port transmit and receive operations occur simultaneously on an active (high) FR framing pulse. Serial-port transmit-channel outputs. 2.048 MHz serial data is transmitted from the transmit registers on these pins. These outputs are in the high-impedance state when not transmitting. DX0 = channel 1; DX1 = channel 2. 8 kHz external serial-port receive-framing input. If external clocking is selected, data is received via the receive pins (DR1 and DR0) on the active (low) FSR input. The falling edge of FSR initiates the receive process, and the rising edge causes the M-986 to process the data. 2.048 MHz serial-port clock. Master clock for transmitting and receiving serialport data. Configured as an input in external clocking mode or output in internal clocking mode. Reset (RS) forces SCLK to the high-impedance state. 8 kHz external serial-port transmit-framing input. If external clocking is enabled, data is transmitted on the transmit pins (DX1, DX0) on the active (low) input. The falling edge of FSX initiates the transmit process, and the rising edge causes the M-986 to internally load data for the next cycle.
EXINT MC MC/PM RS
5 3 27 4
I I I I
WR
31
I/O
XF
28
O
CLKOUT VSS VCC X1 X2/CLKIN DR1 & DR0 FR
6 10 30 7 8 33 & 29 37
O I I O I I O
DX1 & DX0
36 & 35
O
FSR
39
I
SCLK
34
I/O/Z
FSX
38
I
Rev. 3
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M-986-2A1
Serial Port Timing
td (CH-FR) td (DX1-CL) td (DX2-CL) th (DX) tsu (DR) th (DR) tc (SCLK) tf (SCLK) tr (SCLK) tw (SCLKL) tw (SCLKH) tsu (FS) Parameter Internal framing delay from SCLK rising edge DX bit 1 valid before SCLK falling edge DX bit 2 valid before SCLK falling edge DX hold time after SCLK falling edge DR setup time before SCLK falling edge DR hold time after SCLK falling edge Serial port clock cycle time Serial port clock fall time Serial port clock rise time Serial port clock low-pulse duration* Serial port clock high-pulse duration* FSX/FSR setup time before SCLK falling edge Min 20 20 244 20 20 399 220 220 100 Nom 488.28 244.14 244.14 Max 70 4770 30 30 2500 2500 Unit ns ns ns ns ns ns ns ns ns ns ns ns
* The duty cycle of the serial port clock must be within 45% to 55%.
External Frequency Specifications
Parameter Master clock cycle time Rise time master clock input Pulse duration master clock Min 48.818 20 Nom 48.828 5 Max 48.838 10 Unit ns ns ns
tC(MC) tr(MC) tf(MC)
Recommended Operating Conditions
Parameter VCC VSS VIH Supply voltage Supply voltage High-level input voltage Min 4.75 2 3 2.2 0 Nom 5 0 Max 5.25 0.8 0.6 -300 2 70 Unit V V V V V V V A mA C
VIL IOH IOL TA
Low-level input voltage High-level output current (all outputs) Low-level output current (all outputs) Operating free-air temperature
All inputs except CLKIN CLKIN MC/PM All inputs except MC/MP MC/MP
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Rev. 3
M-986-2A1
Coprocessor Interface Timing
Parameter td(R-A) td(W-A) ta(RD) th(RD) tsu(WR) th(WR) tw(RDL) tw(WRL) twr(RBLE) RD low to TBLF high WR low to RBLE high RD low to data valid Data hold time after RD high Data setup time prior to WR high Data hold time after WR high RD low-pulse duration WR low-pulse duration RBLE to RBLE Min 25 30 25 80 60 Nom Max 75 75 80 1 Unit ns ns ns ns ns ns ns ns ms
Reset (RS) Timing
tdis(R) td12 td13 tsu(R) tw(R) Parameter Data bus disable time after RS Delay time from RS to high-impedance SCLK Delay time from RS to high-impedance DX1, DX0 Reset (RS) setup time prior to CLKOUT RS pulse duration Test Conditions RL = 825 CL = 100 pF Min 50 245 Max 75 200 200 Unit ns ns ns ns ns
CLKOUT Timing Parameters
Parameter tc(C) tr(C) tf(C) td(MCC) td 8 CLKOUT cycle time CLKOUT rise time CLKOUT fall time Delay time CLKIN to CLKOUT Delay time CLKOUT to data bus OUT valid RL = 825 CL = 100 pF Test Conditions Min 195.27 25 Nom 195.31 10 8 Max 195.35 60 1/4tc(C)+75 Unit ns ns ns ns ns
Transmitter Characteristics
Parameter FOS TW AS TS Phi Frequency offset Twist Signal amplitude Time skew Power due to extraneous components Test Conditions From nominal High/low Per component Between components Min -7.40 Typ -7.00 Max 1 0.5 -6.60 0 -30 Unit Hz dB dBm0 ms dB
Rev. 3
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M-986-2A1
Reciever Characteristics
Ad And Fd TWd Ton Tint Ti KPLd KPd Td Nt Ni P60 T180 Mt Parameter Detect amplitude No-detect amplitude Detect with frequency offset Detect with twist Tone time Interrupted tone time Tone interpulse time KP long tone detect timeLong detect time KP short tone detect timeLong detect time Tone detect time Noise tolerance Impulse noise 60 Hz tolerance 180 Hz tolerance Modulation products tolerance Test Conditions Per frequency Per frequency From nominal High tone/low tone Reject Reject enabled disabled 1 error in 25,000 digits 1 error in 25,000 digits 1 error in 25,000 digits 1 error in 25,000 digits 2A-B and 2B-A products Min -30 -40 1.5% +5Hz 6 10 10 25 55 30 30 Max -5 -30 -20 -12 81 68 -28 Unit dBm0 dBm0 Hz dB ms ms ms ms ms ms dB dB dBrnc0 dBrnc0 dB
Pin Assignments
8
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M-986-2A1
External Framing Timing Diagrams
Internal Framing Timing
Rev. 3
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M-986-2A1
Reset Timing
Coprocessor Timing
10
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Rev. 3
M-986-2A1
M-986 Dual Channel 4-Wire Interface Application Circuit
Rev. 3
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M-986-2A1
Mechanical Dimensions
Tolerances (inches) Metric (mm) Min Max Min Max A A1 B B1 C D E E1 e L .250 .015 .014 .022 .030 .070 .008 .015 1.98 2.095 .600 .625 .485 .580 .100 BSC .115 .200 6.35 .39 .36 .56 .77 1.78 .20 .38 50.30 53.20 15.24 15.87 12.32 14.73 2.54 BSC 2.93 5.08
Tolerances (inches) A A1 A2 C D D1 Min .165 .090 .062 .020 min .685 .650 .695 .653 Max .180 .20 .083 Metric (mm) Min Max 4.19 4.57 2.29 5.08 1.58 2.11 .51 min 17.40 17.65 16.51 16.66
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Rev. 3
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Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-M986-2A1-R3 (c)Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 7/26/01

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